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How do I test a JFET for Gate-Source Cutoff Voltage on my curve tracer?

Frage:

How do I test a JFET for Gate-Source Cutoff Voltage on my curve tracer?

Antwort:

Gate-Source Cutoff Voltage - VGS(Off)

(aka Pinch-Off Voltage)

What It Is:

Gate-source cutoff voltage is the VGS necessary to reduce ID to a specified value.

On the curve tracer, VDS is forced by the Collector Supply and VGS is forced by the Step Generator.

What The Display Shows:

The display shows VDS on the horizontal axis and ID on the vertical axis.

Specifications are met when at the specified ID, VGS is within the specified min/max limits.

How To Do It:

1. Set controls:

            A: Max Peak Volts to smallest possible value above  the specified VDS

            B: Max Peak Power Watts to the lowest setting that satisfies (ID x VDS)

            C: Horizontal Volts/Div to display VDS between the 5th and 10th horizontal  divisions

            D: Collector Supply Polarity to +Leakage (N-channel) or -Leakage (P-channel)

            E: Vertical Current/Div to display ID between the 5th and 10th vertical divisions   

            F: Step Generator to Voltage

            G: Number of steps to minimum (zero)

            H: Step Generator Polarity to apply reverse bias  (- for N-channel), (+ for P-channel)

            I: Step/Offset Ampl to smallest value possible above the maximum specified VGS

            J: Configuration to (Base/Step Gen, Emitter/Common)

            K: Variable Collector Supply to minimum % (full ccw)

            L: DotCursor ON

2.Apply power to the JFET:

            A: Position the Left/Right switch  as appropriate

            B: Slowly increase the Variable Collector Supply % until the specified VDS is reached

3. Apply gate voltage:

            Press Offset Oppose until ID reaches the specified value

4. Compare to data sheet specifications:

            Check that at the specified ID, VGS is within the specified min/max limits


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