High-speed serial bus architectures are the new norm in today’s high-performance designs. While parallel bus standards are undergoing some changes, serial buses are established across multiple markets – computers, cell phones, entertainment systems, and others – and offer performance advantages, lower cost, and fewer traces in circuit and board designs and layouts.
You might already have experience with first- and secondgeneration serial bus standards, like 2.5 Gb/s PCI Express® (PCIe) and 3 Gb/s Serial ATA (SATA). Engineers are now looking at the requirements in designing to third-generation specifications, including PCI Express 3.0 (8 Gb/s), that are still evolving in working groups.
Serial buses continue to advance with faster edge rates and a narrower unit interval (UI), creating unique, exacting demands on your design, compliance testing, and debug processes. Standards have reached speeds at which you need to be ready for RF analog characteristics and transmission line effects that have a far bigger impact on the design than in the past.
Faster transition times, shorter UIs, different pathway impedances, and noise sources in the amplitude domain all contribute more to bit error rate and add up to engineers needing to take a fresh look at their strategies for connectivity, pattern generation, receiver-side testing, data acquisition, and analysis. Coupling these issues with evolving standards and tighter compliance testing requirements creates a tougher job for companies to quickly get their products to market.
In this primer, we look at the compliance requirements of serial standards, with focus on the issues of next generation standards. After introducing the characteristics of several key standards, we’ll look at the issues you face, including basic tests, and what you need to consider during the compliance testing and debug phases. We’ll address five main areas: connecting to the device under test (DUT), generating accurate test patterns, testing receivers, acquiring data, and analyzing it.
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