TLA5000B Series

Logic Analyzers
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Features & Benefits

  • 500 ps (2 GHz)/32 Mb timing record length to capture intermittent events over a wide time window
  • 125 ps resolution MagniVu™ acquisition simultaneous with timing or state acquisition to find elusive timing problems quickly, without double probing
  • Glitch and setup/hold violation triggering and display to find and display elusive hardware problems
  • 235 MHz state acquisition provides analysis of high-speed synchronous digital circuits
  • iView™ time-correlated digital-analog view to clearly see how analog anomalies are affecting your digital signals
  • 34/68/102/136 channel configurations offer flexible solutions to fit any budget
  • Microsoft Windows XP Professional PC controller provides familiar user interface with network connectivity
  • Remotely control and monitor the TLA over the network using either hosted mode or the built-in Windows XP remote desktop

Applications

  • Digital hardware verification and debug
  • Monitoring and measurement of digital hardware performance
  • Single microprocessor or bus debug

TLA5000B Series Logic Analyzers Combine Debug Power with Simplicity and Affordability

The affordable TLA5000B Series logic analyzers make high-speed timing resolution, fast state acquisition, long record length, and sophisticated triggering available to any digital designer who needs to identify initialization failures, operation crashes, and intermittent operation. For first-time as well as experienced logic analyzer users, the TLA5000B Series is ideal for single-bus timing and state analysis. An intuitive user interface, familiar Windows-based desktop, and OpenChoice® networking and analysis features make the TLA5000B Series logic analyzers easy to network into your design environment.

500 ps timing resolution and 32 Mb record length with simultaneous 125 ps MagniVu timing resolution within each acquisition means you can measure digital signal timing on increasingly faster signals with confidence. With MagniVu timing resolution, find difficult problems such as digital logic errors, glitches, setup/hold violations, and crosstalk quickly. Use setup/hold violation triggering and display to validate setup/hold performance of digital devices.

Today, most designs can have both digital and analog anomalies. With iView™ time-correlated digital-analog view, you’ll clearly see how analog anomalies are affecting your digital signals – right on your logic analyzer display.

Characteristics

General

Characteristic

Description

Number of Channels

(all channels are acquired including clocks)

   TLA5201B

34 channels (2 are clock channels)

   TLA5202B

68 channels (4 are clock channels)

   TLA5203B

102 channels (4 are clock and 2 are qualifier channels)

   TLA5204B

136 channels (4 are clock and 4 are qualifier channels)

Time Stamp

51 bits at 125 ps resolution (3.25 days duration)

Clocking/Acquisition Modes

Asynchronous and Synchronous. 125 ps (8 GHz) MagniVu™ high-speed timing is available simultaneous with all modes

Input Characteristics (with P64xx probes)

Characteristic

Description

Capacitive Loading

   (P6419, P6450)

<0.7 pF typical data/clock

   (P6410, P6434)

2 pF typical data/clock

Threshold Selection Range

From –2.0 V to +4.5 V in 5 mV increments.

Threshold presets include TTL (1.5 V), CMOS (1.65 V), ECL (–1.3 V), PECL (3.7 V), LVPECL (2.0 V), LVCMOS 1.5 V (0.75 V), LVCMOS 1.8 V (0.9 V), LVCMOS 2.5 V (1.25 V), LVCMOS 3.3 V (1.65 V), LVDS (0 V), and user defined

Threshold Selection Channel Granularity

Separate selection for each of the clock/qualifier channels and one per group of 16 data channels

Threshold Accuracy (including probe)

±(100 mV)

Input Voltage Range

   Operating

–2.5 V to 5.0 V

   Nondestructive

±15 V

Minimum Input Signal Swing

   P6410, P6419, P6450

±250 mV

   P6434

±300 mV

Input Signal Minimum Slew Rate

200 mV/ns typical

State Acquisition Characteristics

Characteristic

Description

Maximum State Clock Rate

235 MHz

Maximum State Data Rate

470 Mb/s

State Record Length with Time Stamps (half/full channels)

4/2 Mb , 16/8 Mb, 64/32 Mb

Setup-and-Hold Time Selection Range

16 ns range that may be shifted towards the setup region by 0 ns [+8, -8] ns, 4 ns [+12, -4] ns, or 8 ns [+16, 0] ns

Setup-and-Hold Window

All Channels: 1.5 ns typical

Minimum Clock Pulse Width

   P6434

1.5 ns

   P6410, P6419, P6450

1.25 ns

Demux Channel Selection

Channels can be demultiplexed to other channels through user interface with 8-channel granularity

Timing Acquisition Characteristics

Characteristic

Description

MagniVu™ Timing Resolution

125 ps (8 GHz).

Storage rate adjustable to 250 ps, 500 ps, 1 ns, and 2 ns

MagniVu Timing Record Length

16 Kb per channel, with adjustable trigger position

Timing Resolution (quarter/half/full channels)

500 ps/1 ns/2 ns to 50 ms

Timing Record Length (quarter/half/full channels with time stamps and with or without transitional storage)

8/4/2 Mb, 32/16/8 Mb, 128/64/32 Mb per channel

Timing Record Length with Glitch Storage Enabled

Half of default main record length

Channel-to-channel Skew

1 ns (900 ps typical)

Minimum Recognizable Pulse/Glitch Width (single channel)

   P6410, P6419, P6450

1 ns

   P6434

1.25 ns

Minimum Detectable Setup/Hold Violation

250 ps

Minimum Recognizable Multichannel Trigger Event

Sample period + channel-to-channel skew

Trigger Characteristics

Characteristic

Description

Independent Trigger States

16

Maximum Independent If/Then Clauses per State

16

Maximum Number of Events per If/Then Clause

8

Maximum Number of Actions per If/Then Clause

8

Maximum Number of Trigger Events

18 (2 counter/timers plus any 16 other resources)

Number of Word Recognizers

16

Number of Transition Recognizers

16

Number of Range Recognizers

4

Number of Counter/Timers

2

Trigger Event Types

Word, group, channel, transition, range, anything, counter value, timer value, signal, glitch, setup-and-hold violation, snapshot

Trigger Action Types

Trigger main, trigger MagniVu™, store, don't store, start store, stop store, increment counter, decrement counter, reset counter, start timer, stop timer, reset timer, snapshot current sample, goto state, set/clear signal, do nothing

Trigger Sequence Rate

DC to 500 MHz (2 ns)

Counter/Timer Range

51 bits each (>50 days at 2 ns)

Counter Rate

DC to 500 MHz (2 ns)

Timer Clock Rate

500 MHz (2 ns)

Counter/Timer Latency

2 ns

Range Recognizers

Double bounded (can be as wide as any group, must be grouped according to specified order of significance)

Setup-and-Hold Violation Recognizer Setup Time Range

From 8 ns before to 7.5 ns after clock edge in 125 ps increments

Setup-and-Hold Violation Recognizer Hold Time Range

From 7.5 ns before to 8 ns after clock edge in 125 ps increments

Trigger Position

Any data sample

MagniVu™ Trigger Position

MagniVu position can be set from 0% to 60% centered around the MagniVu trigger

Storage Control (data qualification)

Global (conditional), by state (start/stop), block, by trigger action, or transitional. Force main prefill selection available

iView™ (Integrated View) Capability

Characteristic

Description

TLA Mainframe Configuration Requirements

GPIB-iView (Opt. 1C) requires TLA Application Software V5.0 or greater

 

USB-iView (Opt. 2C) requires TLA Application Software V5.8 or greater

Number of Oscilloscopes that can be Connected to a TLA System

1

External Oscilloscopes Supported

For a complete list of currently supported oscilloscopes that are supported, please visit our website http://www.tektronix.com/iview

TLA Connections

USB, Trigger In, Trigger Out, Clock Out

Oscilloscope Connections

   GPIB-iView

   (Opt. 1C)

GPIB, Trigger In, Trigger Out, Clock In (when available)

   USB-iView

   (Opt. 2C)

USB Device Port, Trigger In, Trigger Out

Setup

iView external oscilloscope wizard automates setup

Data Correlation

After oscilloscope acquisition is complete, data is automatically transferred to the TLA and time correlated with the TLA acquisition data

Deskew

Oscilloscope and TLA data is automatically deskewed and time correlated when using the iView external oscilloscope cable

GPIB-iView External Oscilloscope Cable Length

2 m (6.6 ft.)

USB-iView External Oscilloscope Cable Length

1.8 m (6 ft.)

PC Characteristics

Characteristic

Description

Operating System

Microsoft Windows XP Professional with Multilingual User Interface Pack

Processor

Intel Celeron 2.0 GHz

Chipset

Intel 865G

DRAM

512 MB SDRAM

Sound

16 bit I/O and Mic In port

Hard Drive

≥80 GB

Optical Drive

Internal 24/10/24 CD-RW

Integral Controls

Characteristic

Description

Front-panel Display

   Size

10.4 in. (26.4 cm) diagonal

   Type

Active-matrix color TFT LCD with backlight

   Resolution

1024×768

   Colors

256k

Simultaneous Display Capability

The front-panel and secondary displays can be operated simultaneously using the same resolution. The secondary external display can be used simultaneously using an independent resolution

Front-panel Controls

Special function knobs for instrument control and mini-QWERTY keypad

External Peripheral Interfaces

Characteristic

Description

External Display Port Type

Two female DB15 SVGA

External Display Resolution

Up to 1600×1200 noninterlaced at 16.8M colors

LAN Port Type

10/100Base-T, RJ-45

External Keyboard Port Type

PS2 mini-DIN

External Mouse Port Type

PS2 mini-DIN

Parallel Interface Port Type

Female DB25

Parallel Interface Modes

Centronics mode, EPP (Extended Parallel Port), ECP (Microsoft high-speed mode)

Serial Interface Port Type

Male DB9

Audio Out Port Type

Stereo minijack

Mic In Port Type

Minijack

USB Port

Four USB 2.0

Symbolic Support

Characteristic

Description

Number of Symbols/Ranges

Unlimited (limited only by amount of virtual memory available on TLA)

Object File Formats Supported

IEEE695, OMF 51, OMF 86, OMF 166, OMF 286, OMF 386, COFF, Elf/Dwarf 1 and 2, Elf/Stabs, TSF (TSF is a generic ASCII file format documented in the TLA user manual). If a format is not listed, please contact your local Tektronix representative

External Instrumentation Interfaces

Characteristic

Description

System Trigger Output

Asserted whenever a system trigger occurs (TTL-compatible output, back-terminated into 50 Ω). BNC type connector

System Trigger Input

Forces a system trigger (triggers all modules) when asserted (TTL-compatible, edge-sensitive, falling-edge latched). BNC type connector

External Signal Output

Can be used to drive external circuitry from a module's trigger mechanism (TTL-compatible output, back-terminated into 50 Ω). BNC type connector

External Signal Input

Can be used to provide an external signal to arm or trigger any or all modules (TTL-compatible, level-sensitive). BNC type connector

Power

Characteristic

Description

Voltage Range/Frequency

90-240 V AC at 47-63 Hz

Input Current

5 A maximum at 90 V AC

Power Consumption

300 W maximum

Physical Characteristics

TLA5000B

Dimensions

mm

in.

Height

285

11.2

Width

438

17.5

Depth

288

11.35

Weight

kg

lb.

Net (w/o probes)

12

26

Shipping (typical)

18.5

41

Environmental

Characteristic

Description

Temperature

   Operating

+5 °C to +50 °C

   Nonoperating

–20 °C to +60 °C

Humidity

20% to 80%

   Operating

20% to 80% relative humidity (29 °C maximum wet bulb temperature)

   Nonoperating

8% to 80% (29 °C maximum wet bulb temperature)

Altitude

   Operating

–1,000 ft. to 10,000 ft. (–305 m to 3,050 m)

Safety

UL3111-1, CSA1010.1, EN61010-1, IEC61010-1

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